1. Field of the Invention
This invention relates in general to three state gates and, more particularly, to a noninverting three state gate wherein the Miller capactiance for the high impedance state is substantially reduced.
2. Background Art
Three state gates have an output which is capable of assuming an active high, an active low, or a high impedance state. Generally, most previously known gates having bipolar transistors comprise a push-pull output driver stage, a phase-splitting stage, and an input stage. The push-pull output driver stage comprises a dual transistor arrangement wherein an upper transistor is coupled between a DC voltage supply and an output load and a lower transistor is coupled between the output load and ground. In operation, a high output voltage is realized at the output terminal by turning on the upper transistor and turning off the lower transistor; a low output voltage is realized by turning off the upper transistor and turning on the lower transistor; and a high impedance is achieved by turning off both transistors.
The phase-splitting stage comprises a transistor coupled between the bases of the two output transistors of the output stage that would selectively turn on one of the two output stage transistors. The input stage typically comprises a transistor responsive to an input signal for turning on and off the transistor of the phase-splitting stage. Output enable circuitry is responsive to an output enable signal and is coupled to the collector and base of the phase-splitting transistor for directing current away therefrom, thus turning off both of the upper and lower transistors of the output stage, thereby giving a high impedance at the output terminal.
When a high impedance output is desired and both the upper and lower transistors are off, the base-collector capacitive charge stored on the lower transistor presents spiking problems for the high impedance output. This base-collector capacitive charge, known as Miller capacitance, is multiplied by the beta of the lower transistor. A previously known method of reducing this Miller capacitance includes a first NPN transistor having a collector connected to the base of the lower output transistor and an emitter coupled to ground. A second NPN transistor has its collector connected to the base of the first NPN transistor and is coupled to a voltage supply by a first resistor. The emitter of the second NPN transistor is connected to ground. A third NPN transistor has its collector connected to the base of the second NPN transistor, its base coupled to a voltage supply by a resistor, and its emitter connected to the output enable means. This circuitry, described in more detail in the Detailed Description of the Preferred Embodiment, ensures that the base of the lower output transistor is pulled to a low impedance, i.e., the Miller capacitance of the lower output transistor is pulled to ground through the collector-emitter of the first NPN transistor.
However, this previously known circuitry requires a relatively large amount of current that requires large gate devices and metalization for a monolithically integrated circuit.
Thus, a need exists for an improved three state gate having circuitry for reducing the Miller capacitance for the high impedance state having lower current, faster transitions into and out of the high impedance state, a lighter load for the output enable circuitry and reduced chip area requirements.